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?1 CXA3026Q e94711d92 8-bit 120msps flash a/d converter description the CXA3026Q is an 8-bit high-speed flash a/d converter capable of digitizing analog signals at the maximum rate of 120msps. ecl, pecl or ttl can be selected as the digital input level in accordance with the application. the ttl digital output level allows 1: 2 demultiplexed output. features differential linearity error: 0.5lsb or less integral linearity error: 0.5lsb or less high-speed operation with a maximum conversion rate of 120msps low input capacitance: 21pf wide analog input bandwidth: 150mhz low power consumption: 760mw low error rate excellent temperature characteristics 1: 2 demultiplexed output 1/2 frequency divided clock output (with reset function) compatible with ecl, pecl and ttl digital input levels single +5v power supply operation available surface mounting package pin configuration (top view) structure bipolar silicon monolithic ic applications magnetic recording (prml) communications (qpsk, qam) lcds digital oscilloscopes sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 48 pin qfp (plastic) lead treatment: palladium plating clk/e n.c. clk/t n.c. n.c. dv cc 2 dgnd2 p2d0 p2d1 p2d2 p2d3 clkn/e p2d4 p2d7 p2d6 dgnd1 dv cc 1 dv cc 2 dgnd2 p1d0 p1d1 p1d2 p1d3 p2d5 resetn/e select resetn/t inv clkout dv cc 2 dgnd2 p1d7 p1d6 p1d5 p1d4 reset/e dv ee 3 v rm 1 agnd av cc v in v rm 2 av cc v rm 3 agnd v rt dgnd3 v rb 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 2 3 4 5 6 7 8 9 10 11 12 1
? 2 CXA3026Q absolute maximum ratings (ta = 25 c) unit supply voltage av cc , dv cc 1, dv cc 2 ?.5 to +7.0 v dgnd3 ?.5 to +7.0 v dv ee 3 ?.0 to +0.5 v dgnd3 ?dv ee 3 ?.5 to +7.0 v analog input voltage v in v rt ?2.7 to av cc v reference input voltage v rt 2.7 to av cc v v rb v in ?2.7 to av cc v |v rt ?v rb | 2.5 v digital input voltage ecl ( *** /e * 1 ) dv ee 3 to +0.5 v pecl ( *** /e) ?.5 to dgnd3 v ttl ( *** /t, inv) ?.5 to dv cc 1 v other (select) ?.5 to dv cc 1 v vid * 2 (| *** /e ? *** n/e|) 2.7 v storage temperature tstg ?5 to +150 c allowable power dissipation p d 2 w (when mounted on a glass fabric base epoxy board with 50mm x 50mm, 1.6mm thick) recommended operating conditions with a single power supply with dual power supplies unit min. typ. max. min. typ. max. supply voltage dv cc 1, dv cc 2, av cc +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 v dgnd1, dgnd2, agnd ?.05 0 +0.05 ?.05 0 +0.05 v dgnd3 +4.75 +5.0 +5.25 ?.05 0 +0.05 v dv ee 3 ?.05 0 +0.05 ?.5 ?.0 ?.75 v analog input voltage v in v rb v rt v rb v rt v reference input voltage v rt +2.9 +4.1 +2.9 +4.1 v v rb +1.4 +2.6 +1.4 +2.6 v |v rt ?v rb | 1.5 2.1 1.5 2.1 v digital input voltage ecl ( *** /e) : v ih dgnd3 ?1.05 dgnd3 ?0.5 v : v il dgnd3 ?3.2 dgnd3 ?1.4 v pecl ( *** /e) : v ih dgnd3 ?1.05 dgnd3 ?0.5 v : v il dgnd3 ?3.2 dgnd3 ?1.4 v ttl ( *** /t, inv) : v ih 2.0 2.0 v : v il 0.8 0.8 v other (select) : v ih dv cc 1 dv cc 1 v : v il dgnd1 dgnd1 v vid * 2 (| *** /e ? *** n/e| ) 0.4 0.8 0.4 0.8 v maximum conversion rate fc (straight mode) 100 100 msps (dmux mode) 120 120 msps ambient temperature ta ?0 +75 ?0 +75 c * 1 *** /e and *** /t indicate clk/e and clk/t, etc. for the pin name. * 2 vid: input voltage differential ecl and pecl switching level v i d v i l ( m i n . ) v i h v t h ( d g n d 3 1 . 2 v ) v i l v i h ( m a x . ) d g n d 3
? 3 CXA3026Q block diagram 6 b i t s 2 3 5 8 1 0 1 2 1 3 1 4 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 4 1 r / 2 1 2 6 3 6 4 6 5 1 2 6 1 2 7 1 2 8 1 2 9 1 9 1 1 9 2 1 9 3 2 5 4 2 5 5 r 6 b i t s 9 7 4 r 1 r 2 r r r r r r r r r r r r r r / 2 6 b i t s 6 b i t s 8 b i t s 8 b i t s d e l a y 1 5 4 6 4 7 4 8 s e l e c t d q q 4 5 s e l e c t 1 1 4 3 d g n d 1 d v e e 3 d g n d 2 a g n d a v c c d v c c 2 d v c c 1 i n v d g n d 3 6 v r t v r m 3 v i n v r m 2 v r b v r m 1 c l k / t c l k / e c l k n / e r e s e t n / t r e s e t n / e r e s e t / e t t l o u t l a t c h b t t l o u t l a t c h a 6 - b i t l a t c h + e n c o d e r e n c o d e r c l k o u t n . c . p 2 d 0 p 2 d 1 p 2 d 2 p 2 d 3 p 2 d 4 p 2 d 5 p 2 d 6 p 2 d 7 p 1 d 0 p 1 d 1 p 1 d 2 p 1 d 3 p 1 d 4 p 1 d 5 p 1 d 6 p 1 d 7 ( l s b ) ( m s b ) ( l s b ) ( m s b )
? 4 CXA3026Q pin description and i/o pin equivalent circuit analog ground. separated from the digital ground. analog power supply. separated from the digital power supply. digital ground. digital power supply. digital power supply. ground for ecl input. +5v for pecl and ttl input. digital power supply. ?v for ecl input. ground for pecl and ttl input. no connected pin. not connected with the internal circuits. clock input. clk/e complementary input. when left open, this pin goes to the threshold potential. only clk/e can be used for operation, but complementary input is recommended to attain fast and stable operation. reset input. when the input is set to low level, the built-in clk frequency divider circuit can be reset. resetn/e complementary input. when left open, this pin goes to the threshold voltage. only resetn/e can be used for operation. 3, 10 5, 8 20, 29 32, 41 19, 30 31, 42 12 1 16, 17 18 13 14 48 47 agnd av cc dgnd1 dgnd2 dv cc 1 dv cc 2 dgnd3 dv ee 3 n.c. clk/e clkn/e resetn/e reset/e gnd +5v (typ.) gnd +5v (typ.) +5v (typ.) (with a single power supply) gnd (with dual power supplies) gnd (with a single power supply) ?v (typ.) (with dual power supplies) ecl/ pecl pin no. symbol i i i i i/o standard voltage level equivalent circuit description d g n d 3 d v e e 3 r r 1 . 2 v r r 1 3 1 4 4 8 4 7
? 5 CXA3026Q 15 clk/t clock input. 46 resetn/t ttl ttl vcc or gnd reset input. when left open, this input goes to high level. when the input is set to low level, the built-in clk frequency divider circuit can be reset. 44 inv data output polarity inversion input. when left open, this input goes to high level. (see table 1. i/o correspondence table.) 45 select data output mode selection. (see table 2. operating mode table.) 4.0v (typ.) 11 v rt top reference voltage. by-pass to agnd with a 1 f tantal capacitor and a 0.1 f chip capacitor. v rb + (v rt ?v rb ) 9 v rm 3 reference voltage mid point. by-pass to agnd with a 0.1 f chip capacitor. 7 v rm 2 reference voltage mid point. by-pass to agnd with a 0.1 f chip capacitor. 4 v rm 1 reference voltage mid point. by-pass to agnd with a 0.1 f chip capacitor. 2.0v (typ.) 2 v rb bottom reference voltage. by-pass to agnd with a 1 f tantal capacitor and a 0.1 f chip capacitor. d v c c 1 d g n d 1 1 . 5 v r / 2 r d v e e 3 1 5 4 6 d v c c 1 d g n d 1 d v e e 3 4 4 d v c c 1 d g n d 1 d v e e 3 4 5 r 1 r / 2 c o m p a r a t o r 1 c o m p a r a t o r 6 3 c o m p a r a t o r 6 4 c o m p a r a t o r 1 2 8 c o m p a r a t o r 1 9 1 c o m p a r a t o r 1 2 7 c o m p a r a t o r 1 9 2 c o m p a r a t o r 2 5 5 r r 2 r / 2 r r r r 4 7 9 2 1 1 r i i i i i 4 3 4 2 v rb + (v rt ?v rb ) 4 1 v rb + (v rt ?v rb ) pin no. symbol i/o standard voltage level equivalent circuit description
? 6 CXA3026Q clock output. (see table 2. operating mode table.) 33 to 40 p1d0 to p1d7 port 1 side data output. 21 to 28 p2d0 to p2d7 43 clkout port 2 side data output. 6 v in v rt to v rb i ttl o o o analog input. a v c c c o m p a r a t o r v r e f a g n d d v e e 3 a v c c 6 d v c c 2 d g n d 2 d v c c 1 d g n d 1 1 0 0 k d v e e 3 2 1 2 8 3 3 4 0 4 3 t o t o pin no. symbol i/o standard voltage level equivalent circuit description
? 7 CXA3026Q resolution dc characteristics integral linearity error differential linearity error analog input analog input capacitance analog input resistance analog input current reference input reference resistance reference current offset voltage v rt side v rb side digital input (ecl, pecl) digital input voltage : high : low threshold voltage digital input current : high : low digital input capacitance digital input (ttl) digital input voltage : high : low threshold voltage digital input current : high : low digital input capacitance digital output (ttl) digital output voltage : high : low switching characteristics maximum conversion rate aperture jitter sampling delay clock high pulse width clock low pulse width resetn_clk setup resetn_clk hold time clkout output delay data output delay output rise time output fall time electrical characteristics (dv cc 1, 2, av cc , dgnd3 = +5v, dgnd1, 2, agnd, dv ee 3 = 0v, v rt = 4v, v rb = 2v, ta = 25 c) item symbol min. typ. max. unit conditions e il e dl c in r in i in rref * 3 iref * 4 eot eob v ih v il v th i ih i il v ih v il v th i ih i il v oh v ol fc taj tds tpw1 tpw0 t_rs t_rh td_clk tdo1 tdo2 tr tf 4 0 75 9.7 2 2 dgnd3 ?1.05 dgnd3 ?3.2 ?0 ?5 2.0 ?0 ?00 2.4 120 3 3.2 3.2 3.5 0 4.5 t * 5 6.5 8 21 115 17.4 dgnd3 ?1.2 1.5 10 4.5 7 t + 1 8 2 2 0.5 0.5 50 500 155 28 15 10 dgnd3 ?0.5 dgnd3 ?1.4 +50 0 5 0.8 0 0 5 0.5 6 8 t + 2 10 bits lsb lsb pf k a ma mv mv v v v a a pf v v v a a pf v v msps ps ns ns ns ns ns ns ns ns ns ns v in = 2vp-p, fc = 5msps v in = +3.0v + 0.07vrms v ih = dgnd3 ?0.8v v il = dgnd3 ?1.6v v ih = 3.5v v il = 0.2v i oh = ?ma i ol = 1ma dmux mode clk clk resetn ?clk resetn ?clk (c l = 5pf) dmux mode (c l = 5pf) (c l = 5pf) 0.8 to 2.0v (c l = 5pf) 0.8 to 2.0v (c l = 5pf) * these characteristics are for pecl input,unless otherwise specified.
? 8 CXA3026Q * 5 t = * 6 tps: times per sample * 7 pd = (i cc + i ee ) ?v cc + (v rt ?v rb ) 2 rref table 1. i/o correspondence table dynamic characteristics input bandwidth s/n ratio error rate power supply supply current supply current power consumption i cc i ee pd * 7 150 125 0.4 660 46 40 145 0.6 760 10 ?2 10 ? 10 ? 185 0.8 960 mhz db db tps * 6 tps tps ma ma mw v in = 2vp-p, ?db fc = 120msps, fin = 1khz fs dmux mode fc = 120msps, fin = 29.999mhz fs dmux mode fc = 120msps, fin = 1khz fs dmux mode error > 16lsb fc = 120msps, fin = 29.999mhz fs dmux mode error > 16lsb fc = 100msps, fin = 24.999mhz fs straight mode error > 16lsb { { { { { 1 fc inv 1 d7 d0 d7 d0 0 v in v rt v rm 2 v rb 255 254 . . . 128 127 . . . 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 . . . 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 . . . 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 . . . 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 . . . 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 step item symbol min. typ. max. unit conditions * 3 rref: resistance value between v rt and v rb * 4 iref = v rt ?v rb rref
? 9 CXA3026Q electrical characteristics measurement circuit current consumption measurement circuit v r t v i n v r b a v c c d v c c 1 d v c c 2 d g n d 3 d g n d 2 d g n d 1 a g n d c l k / e d v e e 3 5 m h z p e c l 4 v 1 . 9 5 v 2 v 5 v 5 v i c c i e e integral linearity error measurement circuit differential linearity error measurement circuit c x a 3 0 2 6 q a < b a > b c o m p a r a t o r a 8 t o a 1 a 0 b 8 t o b 1 b 0 b u f f e r c o n t r o l l e r d v m 8 8 1 0 0 0 0 0 0 t o 1 1 1 1 0 v i n + v v s 2 s 1 s 1 : o n w h e n a < b s 2 : o n w h e n a > b sampling delay measurement circuit aperture jitter measurement circuit c x a 3 0 2 6 q o s c 1 f : v a r i a b l e o s c 2 l o g i c a n a l i z e r 1 0 0 m h z 1 0 0 m h z a m p e c l b u f f e r c l k v i n 8 f r 1 0 2 4 s a m p l e s aperture jitter measurement method v i n c l k v i n c l k v r t v r m 2 v r b 1 2 9 1 2 8 1 2 7 1 2 6 1 2 5 s a m p l i n g t i m i n g f l u c t u a t i o n ( = a p e r t u r e j i t t e r ) s ( l s b ) d u d t error rate measurement circuit c o m p a r a t o r a > b p u l s e c o u n t e r c x a 3 0 2 6 q s i g n a l s o u r c e l a t c h l a t c h 1 / 8 + s i g n a l s o u r c e f c 4 1 k h z 2 v p - p s i n w a v e f c v i n c l k c l k 8 1 6 l s b a b where s (lsb) is the deviation of the output codes when the largest slew rate point is sampled at the clock which has exactly the same frequency as the analog input signal, the aperture jitter taj is: taj = s / = s / ( ) ? t ? u 2 256 2 p f
? 10 CXA3026Q description of operating modes the CXA3026Q has two types of operating modes which are selected with pin 45 (select). 1. dmux mode (see application circuit 1-(1), (2) and (3).) set the select pin to vcc for this mode. in this mode, the clock frequency is divided by 2 in the ic, and the data is output after being demultiplexed by this 1/2 frequency divided clock. the 1/2 frequency divided clock, which has adequate setup time and hold time for the output data, is output from the clkout pin. when resetting this 1/2 frequency divided clock, the low level of the reset signal should be input to the resetn pin (pin 46or 48). the reset signal requires the setup time (t_rs 3 3.5ns) and hold time (t_rh 3 0ns) to the clock rising edge because it is synchronized with and taken in the clock. therefore, set the reset signal to low for t_rs (min.) + t_rh (min.) = 3.5ns or longer to the clock rising edge. the reset period can be extended by making the low level period of the reset signal longer because the clock output pin is fixed to low (reset) during the low level period at the clock rising edge. if the reset start timing is regarded as not important, the timing where the reset signal is set from high to low is not so consequence. however, when the reset is released this timing must become significant because the timing is used to commence the 1/2 frequency divided clock. in this case, the setup time (t_rs) is also necessary. see the timing chart for detail. (this chart shows the example of reset for 2t.) the a/d converter can operate at fc (min.) = 120msps in this mode. table 2. operating mode table select v cc gnd dmux mode straight mode 120msps 100msps demultiplexed output 60mbps straight output 100mbps the input clock is 1/2 frequency divided and output. 60mhz the input clock is inverted and output. 100mhz operating mode maximum conversion rate data output clock output
? 11 CXA3026Q 8 b i t s c l k o u t d a t a 8 b i t s c l k o u t d a t a c l k a b c l k a a a a a a a a a a a a a a a c x a 3 0 2 6 q c x a 3 0 2 6 q c l k r e s e t n c l k r e s e t n a b a a a a a a a a a a a a a a a 8 b i t s c l k o u t d a t a 8 b i t s c l k o u t d a t a c l k c x a 3 0 2 6 q c x a 3 0 2 6 q a b c l k r e s e t n c l k r e s e t n c l k r e s e t s i g n a l r e s e t s i g n a l ( r e s e t p e r i o d ) ( r e s e t p e r i o d ) when the reset signal is not used. when the reset signal is used. 2. straight mode (see application circuits 1-(4), (5) and (6).) set the select pin to gnd for this mode. in this mode, data output can be obtained in accordance with the clock frequency applied to the a/d converter for applications which use the clock applied to the a/d converter as the system clock. the a/d converter can operate at fc (min.) = 100msps in this mode. digital input level and supply voltage settings the logic input level for the CXA3026Q supports ecl, pecl and ttl levels. the power supplies (dv ee 3, dgnd3) for the logic input block must be set to match the logic input (clk and reset signals) level. digital input level ecl pecl ttl ?v 0v 0v 0v +5v +5v 5v +5v +5v (1) (4) (2) (5) (3) (6) dv ee 3 dgnd3 supply voltage application circuits table 3. logic input level and power supply settings
? 12 CXA3026Q application circuit 1 (1) dmux ecl input + 5 v ( d ) d g 5 v ( d ) a g d g + 5 v ( a ) 4 v + 5 v ( d ) d g 8 - b i t d i g i t a l d a t a l a t c h 8 - b i t d i g i t a l d a t a l a t c h p 1 d 0 t o p 1 d 7 8 - b i t d i g i t a l d a t a p 2 d 0 t o p 2 d 7 8 - b i t d i g i t a l d a t a e c l r e s e t s i g n a l e c l - c l k d g 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 1 d g + 5 v ( d ) 2 v + 5 v ( a ) 2 a g a g a g a g (2) dmux pecl input + 5 v ( d ) d g + 5 v ( d ) d g 8 - b i t d i g i t a l d a t a l a t c h 8 - b i t d i g i t a l d a t a l a t c h p 1 d 0 t o p 1 d 7 8 - b i t d i g i t a l d a t a p 2 d 0 t o p 2 d 7 8 - b i t d i g i t a l d a t a p e c l - c l k d g 3 4 5 6 7 8 9 1 0 1 1 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 1 d g + 5 v ( d ) 2 + 5 v ( d ) a g d g + 5 v ( a ) 4 v 2 v + 5 v ( a ) a g a g a g a g p e c l r e s e t s i g n a l 1 2 (3) dmux ttl input + 5 v ( d ) d g a g a g + 5 v ( a ) 4 v + 5 v ( d ) d g 8 - b i t d i g i t a l d a t a l a t c h 8 - b i t d i g i t a l d a t a l a t c h p 1 d 0 t o p 1 d 7 8 - b i t d i g i t a l d a t a p 2 d 0 t o p 2 d 7 8 - b i t d i g i t a l d a t a t t l r e s e t s i g n a l t t l - c l k d g 3 4 5 6 7 8 9 1 0 1 1 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 1 d g + 5 v ( d ) 2 v a g + 5 v ( a ) 2 + 5 v ( d ) d g a g a g 1 2
? 13 CXA3026Q (4) straight ecl input + 5 v ( d ) d g + 5 v ( d ) d g 8 - b i t d i g i t a l d a t a l a t c h p 1 d 0 t o p 1 d 7 8 - b i t d i g i t a l d a t a e c l - c l k d g 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 6 4 7 4 8 1 d g + 5 v ( d ) 2 e c l ? t t l d g 4 5 a g a g + 5 v ( a ) 4 v 2 v a g + 5 v ( a ) 5 v ( d ) d g a g a g (5) straight pecl input + 5 v ( d ) d g + 5 v ( d ) d g 8 - b i t d i g i t a l d a t a l a t c h p 1 d 0 t o p 1 d 7 8 - b i t d i g i t a l d a t a p e c l - c l k d g 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 6 4 7 4 8 1 d g + 5 v ( d ) 2 p e c l ? t t l d g 4 5 a g a g + 5 v ( a ) 4 v 2 v a g + 5 v ( a ) + 5 v ( d ) d g a g a g (6) straight ttl input + 5 v ( d ) d g + 5 v ( d ) d g 8 - b i t d i g i t a l d a t a l a t c h p 1 d 0 t o p 1 d 7 8 - b i t d i g i t a l d a t a t t l - c l k d g 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 6 4 7 4 8 1 d g + 5 v ( d ) 2 d g 4 5 a g a g + 5 v ( a ) 4 v 2 v a g + 5 v ( a ) + 5 v ( d ) d g a g a g
? 14 CXA3026Q application circuit 2 straight mode ttl i/o (when a single power supply is used) c l k / e n . c . c l k / t n . c . n . c . d v c c 2 d g n d 2 p 2 d 0 p 2 d 1 p 2 d 2 p 2 d 3 c l k n / e r e s e t n / e s e l e c t r e s e t n / t i n v c l k o u t d v c c 2 d g n d 2 p 1 d 7 p 1 d 6 p 1 d 5 p 1 d 4 r e s e t / e d v e e 3 v r m 1 a g n d a v c c v i n v r m 2 a v c c v r m 3 a g n d v r t d g n d 3 v r b p 2 d 4 p 2 d 7 p 2 d 6 d v c c 1 d v c c 2 d g n d 2 p 1 d 0 p 1 d 1 p 1 d 2 p 1 d 3 p 2 d 5 d g n d 1 a a n a l o g i n p u t a g + 5 v ( a ) 2 v 4 v t t l c l k ( l s b ) p 2 d 0 p 2 d 1 p 2 d 2 p 2 d 3 p 2 d 4 p 2 d 5 p 2 d 6 ( m s b ) p 2 d 7 ( l s b ) p 1 d 0 ( m s b ) p 1 d 7 p 1 d 1 p 1 d 2 p 1 d 3 p 1 d 4 p 1 d 5 p 1 d 6 s h o r t 1 0 f 1 0 f 1 f 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 1 a g a g d g + 5 v ( d ) a g a g 2 4 s h o r t s h o r t t h e a n a l o g s y s t e m a n d d i g i t a l s y s t e m a t o n e p o i n t i m m e d i a t e l y u n d e r t h e a / d c o n v e r t e r . s e e t h e n o t e s o n o p e r a t i o n . i s t h e c h i p c a p a c i t o r o f 0 . 1 f . 1 f application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 15 CXA3026Q dmux mode timing chart (select = v cc ) c l k v i n t t p w 0 t p w 1 n + 3 n + 4 n + 2 n + 5 n + 6 t d s n + 1 n + 7 n n 1 4 . 5 n s ( t y p . ) 2 . 0 v 0 . 8 v n 2 . 0 v 0 . 8 v t d o 1 ? t ? t p 2 d 0 t o d 7 p 1 d 0 t o d 7 t + 1 n s ( t y p . ) n + 1 n + 3 n + 2 c l k o u t r e s e t s i g n a l t _ r s t _ r h t _ r s t _ r h a a 2 . 0 v a a a a 0 . 8 v a a 2 . 0 v a a a a 0 . 8 v a a 2 . 0 v a a a a 0 . 8 v 8 n s ( m a x . ) t d _ c l k 4 . 5 n s ( m i n . ) ( r e s e t p e r i o d ) t d o 2 ; 8 n s ( t y p . ) 6 . 5 n s ( m i n . ) 1 0 n s ( m a x . ) t d _ c l k ; 7 n s ( t y p . ) 8 n s ( m a x . ) 4 . 5 n s ( m i n . )
? 16 CXA3026Q straight mode timing chart (select = gnd) t d s t t p w 1 n + 1 n 1 n n + 2 n + 3 c l k v i n t p w 0 4 . 5 n s ( t y p . ) n 3 n 1 p 2 d 0 t o d 7 p 1 d 0 t o d 7 n n 2 n 4 n 4 n 2 n 1 n 3 n 5 2 . 0 v 0 . 8 v 2 . 0 v 0 . 8 v c l k o u t ( c l k i s i n v e r t e d a n d o u t p u t . ) r e s e t s i g n a l 2 . 0 v 0 . 8 v t d _ c l k ; 7 n s ( t y p . ) t d o 2 ; 8 n s ( t y p . ) 6 . 5 n s ( m i n . ) 1 0 n s ( m a x . ) 4 . 5 n s ( m i n . ) 8 n s ( m a x . )
? 17 CXA3026Q timing of a/d converter and peripheral circuit in the maximum clock rate of the demux mode, the timing of 3 channels of adc clk out in same phase is described in detail as below. for example, the clk out from one of the adc is used as the data latch clock. the clock delay and data delay are showed in the following specification, i.e. td_clk 4.5ns (min.) to 8.0ns (max.) tdo2 6.5ns (min.) to 10ns (max.) these values are considered in all the temperature change and power supply variation. when the maximum clock rate 120msps is used, the set-up time (ts) is seemed to be very small from above specifications. but the 3 channels of adc are in the same circuit board, so that the data out delay and clk out delay will be changed in same trend at the same condition of the temperature change and power supply variation. as a result, 0.5ns of the delay will be faster, when the highest temperature and highest power supply is used. also, 0.5ns of the delay will be later, when the lowest temperature and lowest power supply is used. these delay can be omitted in this case. when ta = 25 c, v cc = +5v, the clock delay and data delay are td_clk 5.0ns (min.) to 7.5ns (max.) tdo2 7.0ns (min.) to 9.5ns (max.) the timing of the data out and clk out with above delay variation is showed in below. consequently, the set-up time for the data latching can be obtained as ts (min.) = 3.5ns. the output delay change of the data out and clk out due to the temperature change and the power supply variation should have the same trend of the delay change, the minimum ts = 3.5ns can be guaranteed at any temperature change and power supply variation. a n a l o g i n p u t r a n a l o g i n p u t g a n a l o g i n p u t b c l k r e s e t 8 b i t 8 b i t 8 b i t 8 b i t 8 b i t 8 b i t p 1 d / o u t p 2 d / o u t c l k o u t v i n c l k r e s e t c x a 3 0 2 6 q p 1 d / o u t p 2 d / o u t c l k o u t v i n c l k r e s e t c x a 3 0 2 6 q p 1 d / o u t p 2 d / o u t c l k o u t v i n c l k r e s e t c x a 3 0 2 6 q g a t e a r r a y l a t c h c l k 8 n s ( = 1 / 1 2 0 m s p s ) t h - r e s e t r e s e t s i g n a l t d _ c l k ( m i n . ) 5 . 0 n s < 4 . 5 n s > t d _ c l k ( m a x . ) 7 . 5 n s < 8 . 0 n s > c l k o u t t d o 2 ( m i n . ) 9 . 5 n s < 1 0 n s > 7 . 0 n s < 6 . 5 n s > t h ( m i n . ) 7 . 5 n s p 1 d / o u t p 2 d / o u t 1 6 n s t d o 2 ( m i n . ) t s ( m i n . ) 3 . 5 n s note: in the timing chart, the values in the brackets < > are included all the temperature change and the power supply variation.
? 18 CXA3026Q notes on operation the CXA3026Q is a high-speed a/d converter which is capable of ttl, ecl and pecl level clock input. characteristic impedance should be properly matched to ensure optimum performance during high-speed operation. the power supply and grounding have a profound influence on converter performance. the power supply and grounding method are particularly important during high-speed operation. general points for caution are as follows. the ground pattern should be as large as possible. it is recommended to make the power supply and ground patterns wider at an inner layer using a multi-layer board. to prevent interference between agnd and dgnd and between avcc and dvcc, make sure the respective patterns are separated. to prevent a dc offset in the power supply pattern, connect the avcc and dvcc lines at one point each via a ferrite-bead filter shorting the agnd and dgnd patterns in one place immediately under the a/d converter improves a/d converter performance. ground the power supply pins (avcc, dvcc1, dvcc2, dv ee 3) as close to each pin as possible with a 0.1 f or larger ceramic chip capacitor. (connect the avcc pin to the agnd pattern and the dvcc1, dvcc2 and dv ee 3 pins to the dgnd pattern.) the digital output wiring should be as short as possible. if the digital output wiring is long, the wiring capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output waveform since the original output slew rate is quite fast. the analog input pin v in has an input capacitance of approximately 21pf. to drive the a/d converter with proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance or parasitic inductance by using a large capacity drive circuit. keeping wiring as short as possible, and using chip parts for resistors and capacitors, etc. the v rt and v rb pins must have adequate by-pass to protect them from high-frequency noise. by-pass them to agnd with approximately 1 f tantal capacitor and, 0.1 f chip capacitor as short as possible. if the clk/e pin is not used, by-pass this pin to dgnd with an approximately 0.1 f capacitor. at this time, approximately dgnd3 ?1.2v voltage is generated. however, this is not recommended for use as threshold voltage v bb as it is too weak. when the digital input level is ecl or pecl level, *** /e pins should be used and *** /t pins left open. when the digital input level is ttl, *** /t pins should be used and *** /e pins left open.
? 19 CXA3026Q c u r r e n t c o n s u m p t i o n v s . a m b i e n t t e m p e r a t u r e c h a r a c t e r i s t i c s t a a m b i e n t t e m p e r a t u r e [ c ] 2 5 1 3 0 2 5 7 5 c u r r e n t c o n s u m p t i o n [ m a ] 1 4 0 1 5 0 1 6 0 1 7 0 c u r r e n t c o n s u m p t i o n v s . c o n v e r s i o n r a t e c h a r a c t e r i s t i c s r e s p o n s e f c c o n v e r s i o n r a t e [ m s p s ] 0 1 3 0 6 0 c u r r e n t c o n s u m p t i o n [ m a ] 1 4 0 1 5 0 1 6 0 1 7 0 1 2 0 d m u x m o d e c l = 5 p f f i n = 1 k h z f c l k 4 a n a l o g i n p u t c u r r e n t v s . a n a l o g i n p u t v o l t a g e c h a r a c t e r i s t i c s a n a l o g i n p u t v o l t a g e [ v ] 2 3 4 a n a l o g i n p u t c u r r e n t [ a ] 1 0 0 2 0 0 0 r e f e r e n c e c u r r e n t v s . a m b i e n t t e m p e r a t u r e c h a r a c t e r i s t i c s t a a m b i e n t t e m p e r a t u r e [ c ] 2 5 1 0 2 5 7 5 r e f e r e n c e c u r r e n t [ m a ] 1 5 2 0 v r t = 4 v v r b = 2 v example of representative characteristics
? 20 CXA3026Q s n r v s . i n p u t f r e q u e n c y r e s p o n s e i n p u t f r e q u e n c y [ m h z ] 1 2 0 5 5 0 s n r [ d b ] 3 0 4 0 5 0 3 0 3 1 0 e r r o r r a t e v s . c o n v e r s i o n r a t e c h a r a c t e r i s t i c s 1 2 0 1 4 0 1 6 0 1 0 6 1 0 7 1 0 8 1 0 9 1 0 1 0 e r r o r > 1 6 l s b f i n = 1 k h z f c l k 4 m a x i m u m c o n v e r s i o n r a t e v s . a m b i e n t t e m p e r a t u r e c h a r a c t e r i s t i c s t a a m b i e n t t e m p e r a t u r e [ c ] 2 5 1 3 0 2 5 7 5 f c m a x i m u m c o n v e r s i o n r a t e [ m s p s ] 1 5 0 1 7 0 f i n = 1 k h z f c l k 4 1 4 0 1 6 0 f c = 1 2 0 m s p s e r r o r > 1 6 l s b e r r o r r a t e : 1 0 9 t p s e r r o r r a t e [ t p s ] f c c o n v e r s i o n r a t e [ m s p s ]
? 21 CXA3026Q CXA3026Q evaluation board description the CXA3026Q evaluation board is a special board designed to maximize and facilitate the evaluation performance of the CXA3026Q. after latching the CXA3026Q output data with a frequency divided clock, the analog signal can be regenerated by a 10-bit high-speed d/a converter. the latched data can also be extracted externally via a 24-pin cable connector. features resolution: 8 bits maximum conversion rate: 120msps (min.) supply voltage: 5.0v dual analog input pins: dir.in: ac coupling input pin amp.in: operational amplifier input pin clock frequency division: 1/1 to 1/16 absolute maximum ratings supply voltage v cc ?.5 to +7.0 v v ee ?.0 to +0.5 v +amp ?.5 to +7.0 v ?mp ?.0 to +0.5 v recommended operating conditions min. typ. max. supply voltage v cc +4.75 +5.0 +5.25 v gnd 0 v v ee ?.50 ?.0 ?.75 v +amp +3 +5 +7 v ?mp ? ? ? v | (+amp) ?(?mp) | 9 10 11 v analog input amp. in ?.75 0 +1.05 v dir. in 1.5 2.0 2.2 vp-p clock input clk. in 0.8 1.0 1.2 vp-p
? 22 CXA3026Q d i r i n c o n 2 a g n d a g n d 5 1 w a m p i n c o n 1 a g n d a g n d 8 2 w ( 2 ) v r b . r 1 v r b v r t . r 2 v r t o f f s e t . r 3 o f f s e t b a v r t v r b s 1 v r t v r b v i n a g n d 1 3 0 w 2 7 0 w 1 k w 3 9 0 w 0 . 1 f c l k i n c o n 3 d g n d d g n d 5 1 w v b b c l k c l k o u t s 2 p e c l / t t l c o u n t e r ( p e c l ) ( p e c l ) 4 ( t t l ) 4 p 1 d 0 t o d 7 p 2 d 0 t o d 7 c x a 3 0 2 6 q ( t t l ) 8 ( t t l ) 8 ( t t l ) 8 ( e c l ) 8 t t l / e c l l a t c h d a c ( t t l ) 8 ( e c l ) 8 t t l / e c l l a t c h d a c ( t t l ) c o n 7 c o n 8 p 1 s i d e d a t a p 2 s i d e d a t a ( e c l ) t t l / e c l f u l l s c a l e . r 4 d / a o u t ( 1 . 0 v ) f u l l s c a l e . r 5 d / a o u t ( 1 . 0 v ) s w 1 s e l e c t d m u x s t r a i g h t s w 2 a / d i n v n o r m i n v s w 3 d / a i n v p 1 s i d e o u t p 2 s i d e o u t c o n 5 a g n d c o n 4 a g n d a m p + a m p v e e g n d v c c c o n 6 1 k w block diagram
? 23 CXA3026Q pin description and i/o level pin no. con1 con2 con3 con4 con5 con6 con7 con8 amp. in dir. in clk. in p1 side out p2 side out v cc gnd v ee +amp ?mp p1 side data p2 side data i i i o o i i i i i o o 0.95vp-p 2.0vp-p 1.0vp-p 0 to ?v 0 to ?v +5.0v 0v ?.0v +5.0v ?.0v ttl ttl 0.8a ?.6a 40ma ?0ma doubles the analog input signal amplitude using the operational amplifier. the input impedance is 50 . ac coupling input. suitable for sine waves and other repeating waveforms. the input impedance is 50 . the CXA3026Q operates at the pecl level clock using the sine wave-to-pecl conversion circuit. the input impedance is 50 . allows the d/a converted waveform of the CXA3026Q port 1 side data to be observed. the output impedance is 50 . allows the d/a converted waveform of the CXA3026Q port 2 side data to be observed. the output impedance is 50 . the inside of the board is divided into analog and digital systems. + side power supply for the operation amplifier. ?side power supply for the operation amplifier. the CXA3026Q port 1 side data output is latched at the frequency divided clock and then output. the CXA3026Q port 2 side data output is latched at the frequency divided clock and then output. symbol i/o standard i/o level current description board adjustments and settings 1. v rb .r1: CXA3026Q v rb voltage adjusting volume. 2. v rt .r2: CXA3026Q v rt voltage adjusting volume. 3. offset.r3: adjusting volume for matching the amp.in input and dir.in input signal ranges to the CXA3026Q input range. 4. full scale.r4: full-scale adjusting volume for the port 1 d/a output. (?v: typ.) 5. full scale.r5: full-scale adjusting volume for the port 2 d/a output. (?v: typ.) 6. s1: switching junction for the dual analog input pins. set as follows according to the input pins used. 7. s2: setting junction for the clock frequency division ratio. the operating speed after latching is determined by the frequency division ratio set here. when set to clk out, it operates according to the CXA3026Q clock output. 8. sw1 select: CXA3026Q output mode selector switch. 9. sw2 a/d inv: CXA3026Q output polarity inversion switch. 10. sw3 d/a inv: d/a converter output polarity inversion switch. junction symbol a b amp.in dir.in open 0.1 f short 10k
? 24 CXA3026Q notes on board operation 1. the factory settings for the CXA3026Q evaluation board are as follows. when using the board in this condition, the input signals should be input at the amplitudes shown below. (the frequency is set as desired.) analog input signal: con1 (amp.in) clock input signal: con3 (clk.in) 0 v c e n t e r , 8 0 0 m v p - p o r l e s s 0 v c e n t e r , 1 . 0 v p - p v rb .r1 = 1.5v v rt .r2 = 3.0v offset.r3 = 2.25v full scale.r4 = ?v full scale.r5 = ?v s1 a ... open, b ... short s2 8 ... short (1/8 frequency division) 2. when the analog signal is input from the con1 (amp.in) pin, ic2:clc404 limits the input dynamic range of the a/d converter's analog input signal according to the +amp and ?mp supply voltages. the power supply for the operational amplifier can also be shifted to +amp = +7.0v and ?mp = ?.0v to allow use with a wider input dynamic range. 3. when the analog input signal is a sine wave or other repeating waveform, the signal can be input from the con2 (dir.in) pin with ac coupling. in these cases, the input dynamic range is not limited by the +amp and ?mp supply voltages, but the v rt level may be limited by ic3:njm3403a. therefore, the power supply for the operational amplifier should be shifted in the same manner as in 2. above. 4. in the evaluation board of the CXA3026Q, clc404 (comlinear) is employed for ic2 to drive the analog input signal. though, clc505 (comlinear) can also be used instead of clc404, there should be a little change in the peripheral circuit in this case.
? 25 CXA3026Q CXA3026Q evaluation board timing chart n n + 1 n + 2 n + 3 0 v 0 v 2 v p - p 1 v p - p a p p r o x i m a t e l y 6 . 0 n s a p p r o x i m a t e l y 9 . 0 n s 0 t o 1 v n 6 n 6 n 4 n 2 n 2 n 4 n 4 n 3 n 2 n 1 ( p e c l ) ( t t l ) ( t t l ) ( t t l ) ( a n a l o g r e g e n e r a t i o n w a v e f o r m ) c o n 4 p 1 s i d e o u t c x a 3 0 2 6 q p 1 s i d e d a t a c x a 3 0 2 6 q c l k c o n 7 p 1 s i d e d a t a c l k c o n 3 c l k i n c o n 2 d i r i n o p e r a t i n g c o n d i t i o n s c x a 3 0 2 6 q o p e r a t i n g m o d e a n a l o g i n p u t s 2 s e t t i n g : s t r a i g h t m o d e : d i r i n p i n i n p u t : 1 / 2 f r e q u e n c y d i v i d e d c l o c k c o n 7 p 1 s i d e d a t a d a t a
? 26 CXA3026Q circuit diagram d g n d c 2 0 0 . 1 f c 1 1 1 f c 2 3 0 . 1 f c 2 5 0 . 1 f a g n d a v c c c 2 2 0 . 1 f a g n d c 2 6 0 . 1 f c 2 4 0 . 1 f c 2 1 0 . 1 f c 1 2 1 f d v c c d g n d i c 3 b n j m 3 4 0 3 a 7 6 5 a g n d r 1 8 5 1 r 1 7 4 3 s 1 a b d i r i n c o n 2 i c 2 c l c 4 0 4 6 2 3 a g n d i c 3 c n j m 3 4 0 3 a 8 1 0 9 c 1 9 0 . 1 f c 1 0 1 f a g n d + a m p r 1 6 2 7 0 a g n d a g n d i c 3 a n j m 3 4 0 3 a 1 2 3 c 1 8 0 . 1 f c 9 1 f a g n d + a m p c 1 6 0 . 1 f c 7 1 f a g n d a m p c 1 7 0 . 1 f c 8 1 f a g n d a m p r 1 2 3 9 0 k r 1 1 2 0 0 k r 1 5 2 7 0 r 1 4 1 3 0 a m p i n c o n 1 r 1 3 8 2 r 1 0 2 2 k r 9 7 . 5 k r 3 1 0 k r 1 2 k r 2 1 k r 7 5 1 0 r 8 5 1 0 a v c c r 6 5 1 a g n d d 1 t l 4 3 1 c p 1 1 4 4 7 c 2 7 0 . 1 f d v c c r 3 0 8 2 c 3 0 0 . 1 f d g n d d g n d r 2 8 8 2 r 2 9 8 2 r 2 5 1 3 0 r 2 6 1 3 0 r 2 7 1 3 0 r 2 2 1 k i c 4 b 1 0 h 1 1 6 ( p e c l ) 6 1 0 9 7 i c 4 a 1 0 h 1 1 6 ( p e c l ) 2 5 4 3 i c 4 c 1 0 h 1 1 6 ( p e c l ) 1 4 1 3 1 2 1 5 d g n d c l k i n c o n 3 c 1 5 0 . 1 r 2 0 1 k r 2 1 3 9 0 r 1 9 5 1 1 1 i c 4 d 1 0 h 1 1 6 ( p e c l ) d g n d r 2 4 1 3 0 r 2 3 8 2 d v c c d v c c d g n d d v c c c 2 8 0 . 1 f d g n d s w 2 s w 1 d / a i n v a / d i n v s e l e c t d v c c c 2 9 0 . 1 f a m p + a m p a v e e d v e e a g n d d g n d a v c c d v c c v c c g n d v e e a m p + a m p c 6 3 3 f c 1 3 3 f c 2 3 3 f l 1 l 2 l 3 l 4 l 5 l 6 c 3 3 3 f c 4 3 3 f c 5 3 3 f c 3 3 0 . 1 f d g n d d g n d d v c c c 3 4 0 . 1 f 2 3 4 5 6 7 9 1 1 1 2 1 3 1 4 1 5 c l k s 1 d 0 s 2 d 1 d 2 d 3 q 0 q 1 q 2 q 3 c o u t i c 5 1 0 h 1 3 6 ( p e c l ) s w 3 c o n 6 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 6 3 5 3 4 3 1 3 2 3 3 4 0 3 9 3 8 3 7 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 c l k / e n . c . n . c . n . c . d v c c 2 d g n d 2 p 2 d 0 p 2 d 1 p 2 d 2 p 2 d 3 c l k n / e c l k / t r e s e t n / e s e l e c t i n v c l k o u t d v c c 2 d g n d 2 p 1 d 7 p 1 d 6 p 1 d 5 p 1 d 4 r e s e t / e r e s e t n / t p 1 d 3 d v c c 2 d g n d 2 d g n d 1 d v c c 1 p 1 d 2 p 1 d 1 p 1 d 0 p 2 d 7 p 2 d 6 p 2 d 5 p 2 d 4 i c 1 c x a 3 0 2 6 q d v e e 3 v r b a g n d v r m 1 a v c c a v c c v r m 3 a g n d v r t d g n d 3 v i n v r m 2 p 1 d 0 p 1 d 1 p 1 d 2 p 1 d 3 p 1 d 4 p 1 d 5 p 1 d 6 p 1 d 7 c l k o u t d / a i n v p 2 d 0 p 2 d 1 p 2 d 2 p 2 d 3 p 2 d 4 p 2 d 5 p 2 d 6 p 2 d 7 1 / 1 6 1 / 8 1 / 4 1 / 2 c l k n c l k d g n d a g n d a g n d
? 27 CXA3026Q r 4 6 6 2 0 c 3 2 0 . 1 f d g n d d g n d d g n d d v c c r 3 1 8 2 r 3 4 1 3 0 r 3 2 8 2 r 3 5 1 3 0 r 3 3 8 2 r 3 6 1 3 0 d g n d 1 3 1 4 1 6 1 7 1 8 1 9 1 2 2 3 4 7 8 9 1 1 1 i n 8 o u t 8 2 0 1 0 i n 7 o u t 7 i n 6 o u t 6 i n 5 o u t 5 i n 4 o u t 4 i n 3 o u t 3 i n 2 o u t 2 i n 1 o u t 1 s d g n d s 2 1 / 1 1 / 2 1 / 4 1 / 8 1 / 1 6 c l k o u t 1 3 1 4 1 5 1 6 1 7 1 9 2 0 2 1 2 2 2 3 2 4 2 3 4 8 9 1 0 1 1 1 2 1 d 0 d 1 d 2 d 3 q 0 q 1 q 2 q 3 d 4 d 5 d 0 n d 1 n d 2 n d 3 n d 4 n d 5 n q 4 q 5 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 3 4 5 6 7 8 9 1 1 1 2 1 1 d 1 q 2 d 2 q 3 d 3 q 4 d 4 q 5 d 5 q 6 d 6 q 7 d 7 q 8 d 8 q o c c l k 2 4 7 y 1 1 0 b 5 6 1 5 1 3 1 4 1 2 3 1 a 1 y 1 y 2 y 2 y 3 y 3 y 4 y 4 a 2 a 3 a 4 r 5 0 6 2 0 d v e e d v e e d g n d c 4 6 0 . 1 f r 4 9 6 2 0 c 4 5 0 . 1 f d v e e d g n d r 3 8 8 2 r 3 7 8 2 r 4 0 1 3 0 r 3 9 1 3 0 c 5 4 0 . 1 f r 5 2 k r 4 4 1 k r 4 5 2 7 0 a g n d d 3 t l 4 3 1 c p a g n d a v e e c 5 5 0 . 1 f c 1 4 1 f c 5 6 0 . 1 f d g n d p 2 s i d e o u t c o n 5 d v e e c 5 1 0 . 1 f r 4 2 k r 4 2 1 k r 4 3 2 7 0 a g n d d 2 t l 4 3 1 c p a g n d a v e e c 5 2 0 . 1 f c 1 3 1 f c 5 3 0 . 1 f d g n d p 1 s i d e o u t c o n 4 d v e e 1 3 1 4 1 6 1 7 1 8 1 9 1 2 2 3 4 7 8 9 1 1 1 a g n d 2 0 1 0 v r e f a v e e n c o u t d g n d i n v 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 5 6 1 5 a g n d n c n c n c n c n c d v e e c 5 0 0 . 1 f d g n d r 4 1 6 2 0 d v e e i c 1 0 m b 7 6 7 i c 1 1 1 0 h 1 2 4 1 3 1 4 1 6 1 7 1 8 1 9 1 2 2 3 4 7 8 9 1 1 1 a g n d 2 0 1 0 m s b v r e f d 2 a v e e d 3 n c d 4 o u t d 5 d g n d d 6 i n v d 7 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 5 6 1 5 a g n d n c n c n c n c n c d v e e d 8 d 9 c l k n l s b n c n c c l k i c 1 2 c x 2 0 2 0 1 - 1 i c 1 3 c x 2 0 2 0 1 - 1 i c 7 7 4 a s 5 7 4 i c 8 1 0 0 3 9 0 o e v b b c l k o u t d / a i n v p 2 d 0 p 2 d 1 p 2 d 2 p 2 d 3 p 2 d 4 p 2 d 5 p 2 d 6 p 2 d 7 1 / 1 6 1 / 8 1 / 4 1 / 2 c l k n c l k 1 2 i c 1 4 7 4 a l s 3 4 d g n d 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 3 4 5 6 7 8 9 1 1 1 2 1 1 d 1 q 2 d 2 q 3 d 3 q 4 d 4 q 5 d 5 q 6 d 6 q 7 d 7 q 8 d 8 q o c c l k i c 6 7 4 a s 5 7 4 p 1 d 0 p 1 d 1 p 1 d 2 p 1 d 3 p 1 d 4 p 1 d 5 p 1 d 6 p 1 d 7 p 1 d 0 p 1 d 1 p 1 d 2 p 1 d 3 p 1 d 4 p 1 d 5 p 1 d 6 p 1 d 7 c o n 8 p 2 s i d e d a t a c 3 9 0 . 1 f d g n d d v c c 1 2 2 5 2 6 i c 1 5 7 4 a l s 3 4 i c 1 6 7 4 a l s 3 4 1 0 8 6 4 2 1 2 1 0 8 1 1 9 5 3 1 1 3 1 1 9 p 2 d 0 p 2 d 1 p 2 d 2 p 2 d 3 p 2 d 4 p 2 d 5 p 2 d 6 p 2 d 7 p 2 d 0 p 2 d 1 p 2 d 2 p 2 d 3 p 2 d 4 p 2 d 5 p 2 d 6 p 2 d 7 1 3 1 4 1 6 1 7 1 8 1 9 1 2 2 3 4 7 8 9 1 1 1 i n 8 o u t 8 2 0 1 0 i n 7 o u t 7 i n 6 o u t 6 i n 5 o u t 5 i n 4 o u t 4 i n 3 o u t 3 i n 2 o u t 2 i n 1 o u t 1 s r 4 8 6 2 0 d v e e d v e e c 4 4 0 . 1 f r 4 7 6 2 0 c 4 3 0 . 1 f d g n d i c 9 m b 7 6 7 c o n 7 p 1 s i d e d a t a c 3 5 0 . 1 f d g n d d v c c d g n d 1 2 2 5 2 6 i c 1 4 7 4 a l s 3 4 i c 1 5 7 4 a l s 3 4 6 4 2 1 2 1 0 8 6 4 5 3 1 1 3 1 1 9 5 3 p 1 d 0 p 1 d 1 p 1 d 2 p 1 d 3 p 1 d 4 p 1 d 5 p 1 d 6 p 1 d 7 a g n d a g n d 1 1 m s b d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 c l k n l s b n c n c c l k
? 28 CXA3026Q component list no. product name function ic1 CXA3026Q 8-bit a/d converter ic2 clc404aje op-amp ic3 njm3403am op-amp ic4 mc10h116l ecl buffer ic5 mc10h136l ecl countor ic6, 7 74as574n ttl latch ic8 100390 pecl ? ttl conversion ic9, 10 mb767p ttl ? ecl conversion ic11 mc10h124l ttl ? ecl conversion ic12, 13 cxa20201a-1 10-bit d/a converter ic14 to 16 74als34 ttl buffer d1 to 3 tl431cp shunt regulator sw1 to 3 ate1d-2f3-10 toggle switch s1, 2 jx-1 short pin con1 to 5 01k0315 bnc connector con6 tj-563 power supply connector con7, 8 (fap-2601-1202) flat cable connector l1 to 6 zbf503d-00 ferrite-bead filter c1 to 6 tantal capacitor 33 f c7 to 12 tantal capacitor 1 f c15 ceramic capacitor 0.1 f all parts other than those listed above chip capacitor 0.1 f no. product name function r2 rj-5w-1k 1k volume resistor r1, 4, 5 rj-5w-2k 2k volume resistor r3 rj-5w-10k 10k volume resistor r46 to 50 rgld4x621j 620 network resistor r6, 18, 19 frd-25sr (0.25w) 51 r7.8 frd-25sr (0.25w) 510 r9 frd-25sr (0.25w) 7.5k r10 frd-25sr (0.25w) 22k r11 frd-25sr (0.25w) 200k r12 frd-25sr (0.25w) 390k r13, 23, 28 to 33, 37, 38 frd-25sr (0.25w) 82 r14, 24 to 27, 34 to 36, 39, 40 frd-25sr (0.25w) 130 r15, 16, 43, 45 frd-25sr (0.25w) 270 r17 frd-25sr (0.25w) 43 r20, 22, 42, 44 frd-25sr (0.25w) 1k r21 frd-25sr (0.25w) 390 r41 frd-25sr (0.25w) 620 * con7 and 8 are not mounted when boards are shipped. (manufacturer: yamaichi electronics co., ltd.) component side silk diagram 74als34 74als34 74als34 CXA3026Q/aq CXA3026Q/aq evaluation board
? 29 CXA3026Q component side pattern diagram solder side pattern diagram
? 30 CXA3026Q package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e m p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e w e i g h t e p o x y r e s i n s o l d e r / p a l l a d i u m p l a t i n g c o p p e r / 4 2 a l l o y 4 8 p i n q f p ( p l a s t i c ) 1 5 . 3 0 . 4 1 2 . 0 0 . 1 + 0 . 4 0 . 8 0 . 3 0 . 1 + 0 . 1 5 0 . 1 2 1 3 2 4 2 5 3 6 3 7 4 8 1 1 2 2 . 2 0 . 1 5 + 0 . 3 5 0 . 9 0 . 2 0 . 1 0 . 1 + 0 . 2 1 3 . 5 0 . 1 5 0 . 1 5 0 . 0 5 + 0 . 1 q f p - 4 8 p - l 0 4 * q f p 0 4 8 - p - 1 2 1 2 - b 0 . 7 g n o t e : p a l l a d i u m p l a t i n g t h i s p r o d u c t u s e s s - p d p p f ( s o n y s p e c . - p a l l a d i u m p r e - p l a t e d l e a d f r a m e ) .

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